Abstract:
The gap between processor and memory speeds is increasing day
by day. This situation makes it imperative to use effective caches or
other structures between CPUs and DRAMs. The traditional measures
of the quality of a caching strategy have been the aggregate hit rate and
the execution time of a benchmark, but these measures are no longer
sufficient. They provide no insight into dynamic programme behaviour
and little guidance in designing a multi-level memory hierarchy.
Current caches are designed primarily using ad hoc experimentation
and commonly accepted rules-of-thumb: there is no systematic
experimental methodology, and there is only fragmented theory to
guide the design.
This demands evolution of new methods for evaluating memory
system designs before they are implemented in hardware. One such
method, trace-driven memory simulation, has been the subject of
intense interest among researchers and has, as a result, enjoyed rapid
development and substantial improvements during the past decade.
This project report surveys and analyzes these developments by
establishing criteria for evaluating Cache Designs for Multiprocessor
based Environments using trace-driven simulation method, and then
applies these criteria to describe, categorize and recommend optimal
combinations of Cache Designs basing on user discretion.
Besides, it provides an analysis methodology that supports cache
hierarchy design theoretically and subsequently leads towards the
development of mathematical and software tools that accompany this
methodology.
In doing so it discusses the strengths and weaknesses of different
approaches and uses One Pass Stack based Trace Driven Simulation
method for application of Cache Coherence Protocols, to recommend
best, appropriate and user defined design, when all criteria, including
accuracy, speed, memory, flexibility, portability, ease-of-use and
expense are considered.
