Abstract:
A Software Defined Radio (SDR) has three parts namely RF section, IF section and Baseband section. The project deals with the IF section. Digital down convertor (DDC) and Digital up convertor (DUC) are extensively used in the radio systems. They are more popular than their analogue counterparts because of small size, low power consumption and accurate performance. We have chosen Field Programmable Gate Array (FPGA) for implementation of design because of their real time and high speed processing.
FPGA are the modern-day technology for building a breadboard or prototype from standard parts. Programmable logic blocks and programmable interconnects allow the same FPGA to be used in many different applications because of their reconfigurability. The DDC converts the signal at the output of analog to digital convertor (ADC), centered at the intermediate frequency (IF), to complex baseband signal. Similarly, the DUC converts a baseband signal to a passband IF signal.
The developed prototype has been tested on software by simulating it on the System Generator of Xilinx ISE Design Suite 12.3. Verilog Code was tested successfully on Spartan 3e-1600 FPGA Kit.
