Abstract:
Digital computing is the requirement of every embedded system; Computing Engineering is the domain, which handles design and analysis of computing devices. Emphasis is done on designing microprocessor which is the main component of the system.
Our processor is designed on 32 bit MIPS pipelined architecture to process seventeen instructions in a multi cycle environment. Each instruction is 32 bit large each register and functional units are intended to perform processing on 32 bit inputs. Instructions are broken down into series of steps depending upon the instruction type and its process. The longest instruction will be processed in five stages. Advantage of this approach will be the less usage of hardware. The design contains no structural hazards because all the processes are forward going. The forwarding and hazard detection units are implemented to cater-for the data conflicts and operand matching for increased throughput. The processor also includes the branch prediction in decode unit which results in least wastage of clock cycles. the instruction flushing is also done in case of branch and jump instruction to remove the instruction already in pipeline below the jump instruction in program memory.
