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C Compiler for a Parallel Processor

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dc.contributor.author Kamal, Ahsan
dc.contributor.author Ahmad, Husain
dc.date.accessioned 2020-11-11T09:07:32Z
dc.date.available 2020-11-11T09:07:32Z
dc.date.issued 2002-04
dc.identifier.other PCS-48
dc.identifier.uri http://10.250.8.41:8080/xmlui/handle/123456789/11443
dc.description.abstract In this dissertation, we present a dual-module C compiler for the Media Engine (ME-2), being developed in Communications Enabling Technology (CET). The first module takes the C code and converts it into the serial assembly, referred hereon as Front-end Serial Assembly Generator (FSAG). We have only implemented a minimal functionality prototype of FSAG, whereas in actuality the GNU C compiler is being used as the serial code generator. The second module is the Serial Assembly Optimizer (SAO). This module makes use of advanced optimization techniques to generate a parallel and optimized code. en_US
dc.language.iso en en_US
dc.publisher MCS en_US
dc.title C Compiler for a Parallel Processor en_US
dc.type Technical Report en_US


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