Architecture and Digital Design of a flexible Correlation filter Processor

Abstract

Dedicated design for pattern recognition techniques can provide processing at higher speed, .Many Real time digital designs provide single functionality, but where speed, scalability and flexibility is required more extensive research is demanded. These special purpose and Application specific designs can provide real time procession for many applications. In this thesis the challenges, problems and design for a correlation patteren recognition processor is presented, The design is based on fixed point representation of binry numbers, further the fixed point representation is used to represent complex numbers as correlation filters are designed in frequency domain. The presented design is an educational purposes design, which provides mechanism to handle matrices on chip and also is capable of performing simple matrices operation like arithmetic and matrix handling. The matrices are represented with simple identifiers and using application specific micro instruction provided in the design assist in processing of many complex operations which are useful for solving bigger problems when summed up to gather in a meaning full manner. The design was successfully implemented and tested using VHDL language using Xilinx tool. The objective of this work was to get an area & time efficient architecture that can be used as a standalone processor with built in all resources necessary for an embedded pattern recognition application.