Network-on-Chip based Application Speci c Processors for Frequent Pattern Mining Algorithms

Abstract

Technological advancements in the recent past have seen to the rise of data availability as a result of low cost storage devices and the advent of e-enabled systems in daily life. These factors have played a pivotal role in enhancing the pace at which data mining and machine learning have progressed. Data mining and machine learning algorithms have become an integral part of major elds of engineering and sciences covering medical diagnostics, costumer behavior and trend analysis, sentimental analysis, game playing, house hold, rescue and other such robotics. The bottleneck in the application of data mining and machine learning algorithms in every day task has been gap between the data growth and the performance of algorithms. Various machine learning and data mining algorithms have inherent parallelism which makes them a suitable target for parallel implementation. Parallel implementations on hardware platforms can help in increasing the timing performance of the algorithms. In this dissertation, network on chip based application speci c architecture for data mining applications have been proposed. We have targeted k-means and apriori algorithm for parallel implementations. These algorithms are among the popular and widely used algorithms in the eld of machine learning and data mining. We have proposed a multiple elements based parallel framework for improved e ciency of these algorithms. The multiple elements of the framework work in a collaborative environment where each element process on independent data whereas they share their results with each other for completion of iteration. While sharing of results with each other the traditional bus based connection interfaces fail to provide a scalable interface. In order to enhance the scalability and throughput of the proposed model, a Network-on-Chip (NoC) based interconnect model has been integrated in the proposed multiple element framework. Furthermore, to e ectively make use of the NoC platform an irregular NoC interconnect model is also proposed that has been integrated with our proposed multiple element framework.