FPGA Framework Adaptation for Network on System Based Embedded System

Abstract

The increasing demand for more processors within Multiprocessor systems-on-chips (MPSoCs) results in a trend to shift from 32-bit bus-based embedded systems towards Network-on-Chips (NoC). NoC can overcome the problems caused by long wires in communication. NoC provides high bandwidth by distributing the propagation of delay across multiple switches, thus resulting in parallel signal transmission. Furthermore, they allow increasing number of cores on a single chip without significantly increasing area. High end embedded systems with multiple hybrid processors generally suffer performance issues like low throughput and backpressure due to bandwidth sharing between multiple data streams. Inter-processor communication between multiple hybrid processors is the biggest issue faced by designers of high end communication systems. This thesis presents a novel Network-on-System (NoS) architectural concept to improve the throughput of hybrid processors based high end embedded systems. Every programmable hybrid processor has multiple peripheral interfaces. In most applications, all of these interfaces are never used and are available for communication with other devices. In this thesis, interfaces and operations of the blocks in the NoC are defined through block diagrams and algorithmic state machines. Verification of these blocks is also performed on computer environment via simulations tools.