IMAGE RECOGNITION USING PARALLEL NEURAL ARCHITECTURE

Abstract

This research focuses on parallel implementation of image recognition by adopting an Optimal Mapping and Hybrid Parallel Training (HPT) scheme to train Multilayer Per ceptron (MLP) neural network with Back Propagation (BP) algorithm on High Perfor mance Cluster (HPC). Network decomposition technique is used to break down dataset over the available processors and to train each part-network with our proposed HPT scheme to drive out the communication overhead during parallel training phase of BP algorithm. We used Message Passing Interface (MPI) and Posix Threads (PThreads) for HPT of BP algorithm at distributed and shared memory architecture level respec tively. We derived the closed form expression of parallel training time, based on time expression computed performance parameters like speedup and efficiency and com pared our results with the ones with previously reported Hybrid Partitioning (HP) schemes. Various well known image recognition benchmarking problems have been simulated to evaluate the proposed scheme. Analytical and experimental results show that our proposed scheme takes less training time, is more efficient and required less memory space than other HP schemes. The functional verification of simulated image recognition problem has also been done using Light Efficient Network Simulator (LENS). We devised a novel pre-processing scheme to reduce the size of input dataset, thus reducing the size of underlying neu ral network. Each pixel at the input layer is represented with a single value, which requires less memory space and thus is computationally more efficient. We evaluated the training performance by changing number of neurons in input layer, with varying number of hidden layers and by altering the learning rate. We also collaborated with the SpiNNaker Project at the University of Manchester to simulate our proposed technique on SpiNNaker Massively Parallel CMP System.