Design Space Exploration of ASIP Architecture for various Machine Learning Algorithms (K-NN, K-mean, PAM)

Abstract

Machine learning (ML) algorithms play have become a great importance in every field of life with the advancement in technology. These algorithms are abundantly used in various domains ranging from healthcare, security and wireless sensor networks [1]. With the increase in data availability, these algorithms tend to show timing complexity, which becomes a bottleneck specially in edge computing. Researchers have proposed various solutions to provide high throughput, speed up and efficient deigns of such algorithms keeping edge computing platforms in mind. Variants of Application Specific Processors to Application Specific Instruction Set Processor have been found in research for implementation of ML algorithms (K-NN, NN) on hardware. Thus providing bases for designing a hardwired IP core or Application Specific Instruction Set Processor to implement ML algorithms. ASIP are a much flexible option than hardwired IP Core as they can execute a set of domain algorithms. In this regard, various ASIP implementations have already been proposed for K-NN and Neural Networks (NN) to improve their execution time/energy efficiency etc. In our work, we propose to design an ASIP for various clustering and classification algorithms. The designed ISA will follow the RISC scheme comprising of instructions capable of handling multiple classification and clustering algorithms. Our purpose is to design an ASIP which make these clustering algorithms fast in terms of using less area, higher frequency and low power consumption.