Exploring Design of Class A Radio Frequency Power Amplifier using LDMOS

Abstract

The purpose of this thesis is to investigate the capability of a Class A Radio Frequency Power Amplifier (RFPA) in high efficiency and high power applications in comparison to more popular topologies such as Class AB, J, F etc. The basic approach being pursued is the analysis of the Class A operation using the harmonic termination approach typically seen in before-mentioned classes. Using the well-known load-line theory, a rudimentary Class A RFPA is first designed which is then subsequently improved, mainly by over-driving the RFPA into a harmonically tuned load, to deliver high efficiency along with maximum possible output power. The device used was a LDMOS transistor “AFT27S010N” by NXP. The design process included a negative current peaking phenomenon which is suspected to be unique to devices consisting of supplementary circuitry as part of their internal physical model. Simulated peak output power came out to be around 42 dBm with a drain efficiency of 70% and a PAE of 66.7%. The design was then implemented on a 0.3mm thick FR-4 substrate. Upon measurement, a peak output power of 39.4 dBm and a drain efficiency of 43% was achieved. The apparent mismatch between the simulated and actual performance resulted due to certain limitations in the implementation of the design; the ruggedness of the design concept itself remains undeterred.