A Model-Driven Framework for Embedded Systems Design Verification through Portable Test & Stimulus Standard (PSS)

Abstract

System on Chip (SOC) verification starts when each component/subsystem of the SOC is unit tested separately. These unit-level tests may be written using different languages/platforms. When these components are integrated on a single chip to form a SOC, these unit-level tests can no more be used for system-level verification. ACCELLERA Portable Test & Stimulus Standard (PSS) fills out this gap by providing a single representation of test intent through which tests written at different levels and in different technologies become portable from block to IP level, from subsystem to system level, and from one design configuration to the other. The only bottleneck here is that PSS itself lies at a low level. i.e., we need to model our test intent either using a Domain Specific Language (DSL) or using C/C++. In both of these cases, a test engineer has to write a low-level source code to model the test intent. The current study is aimed to provide a GUI-based tool (PSS Architect) that provides an intuitive user interface by providing all necessary PSS modeling artifacts through drag and drop. Finally, the PSS source code can be easily generated using PSS Architect with a single click. This PSS code can be further used in PSS-supported tools such as DVT-Eclipse. DVT-Eclipse then processes the PSS Code and generates legal test scenarios and corresponding UVM sequences to execute these scenarios. In the end, the proposed design verification framework is verified with the help of two bench-mark case studies. The analysis of the results shows that the proposed framework provides a higher abstraction level in an intuitive way to generate PSS.