Unified Optimization Model for Efficient Resource Utilization on FPGA

Abstract

To maximize the design solution, this study proposes a unique approach for mapping diverse DSP algorithms with multiple design possibilities on to available target hardware platforms. There are several methods to implement a specific algorithm in any design; these different design alternatives are dependent on the algorithm's modular throughput. The resources for each sub-module may be estimated by including different options that correspond to the throughput; this allows the total resources required by the algorithm to be computed during the design process. If the target device has already been chosen, resource use by each choice may be calculated while keeping the available resources in mind for proper algorithm mapping. If the target device is not pre-selected, a suitable platform/device can be chosen based on the throughput criteria and resources necessary. A mathematical model for optimization has been devised. The issue is initially represented as a problem of integer programming. To map a design option, different restrictions have been created. The integer programming issue is solved using a linear programming solution tool, and the design alternative for each sub-module in terms of resource utilization is found as a result. The resources specify the cost of the target device, therefore the cost can be evaluated right at the start of the algorithm design. This model is implemented on a WCDMA communication receiver, and it estimates the resources necessary for complete implementation and determines a viable target platform based on the constraints/design options utilized in module construction. This model optimizes the need based on speed, area, or other constraints.