Abstract:
Due to the rapid changing and flexibility of Wireless Communication protocols, there is a desire to move from hardware to software/firmware implementation in DSPs. High data rate requirements suggest highly optimized firmware implementation in terms of execution speed and high memory requirements. This work suggests optimization levels for the implementation of a viable Viterbi decoding algorithm on a commercial off-the-shelf DSP. Viterbi is a popular decoding algorithm employed in building up many communication systems because of its robustness and ability to detect and correct most of the transmission errors. Optimizing this algorithm to achieve maximum execution speed and minimum possible memory usage is the focus of our research. Different Logic and Code optimization techniques have been applied and discussed throughout the document. With an aim of producing an improved design (in terms of execution speed and memory requirements), the proposed system is able to deliver a data rate of 1.7 Mbps on a clock frequency of 600MHz, for a constraint length (i.e. K=7).
