Design and Evaluation of Approximate Arithmetic Dividers and Square Root Units for Resource-Constrained Hardware

Abstract

Approximate computing is an emerging field which aspires to improve the resource efficiency of DSP systems. It targets the inherent error resilience of compute-intensive applications to reduce the hardware resources at the expense of controlled errors, without affecting the perception of output quality. This intrinsic error-tolerance is prevalent in a wide variety of compute-intensive applications such as machine learning, data mining, and image processing. Arithmetic operations constitute a major part of such applications, thus rendering the approximation of these units a paramount priority for researchers. Among the basic arithmetic units, divider and square root exhibit the highest complexity and constitute the most hardware resources. Over the latter half of the last decade, much research has been conducted into the approximation of dividers, leading to several state-of-the-art designs. One aspect lacking in literature regarding these designs is their effective evaluation with reference to the corresponding commercial units as these dividers are predominantly compared to single-cycle accurate design. However, evidence suggests that commercial vendors such as Intel and AMD implement sequential designs. In this regard, this thesis presents HDL models for commercially-preferred sequential dividers using accurate division algorithms which include restoring, non-restoring, SRT, Newton-Raphson and Goldschmidt methods, for both integer and Floating-Point (FP) operands. These models are then used to compare to the log-based approximate INZeD (integer) and FaNZeD (FP) dividers for hardware metrics including FPGA resources (equivalent to area on ASIC), power, delay and latency. In light of the significant results of the log-based approximation scheme for dividers, the same is pursued for the approximation of square root, which is a novel prospect. A log-based integer square root design, incorporated with an empirically-deduced error-reduction mechanism, is also proposed in this thesis. The proposed design conforms to the norms of an approximate arithmetic unit by ensuring the provision of least inaccuracy with most resource-efficiency, along with error-configurability. The error and hardware characteristics of the proposed design are compared to those of accurate, as well as other approximate units found in literature, resulting in 3.9× reduced power consumption and 8.4× improved energy efficiency as compared to accurate restoring array square root. Furthermore, evaluation based on image processing applications shows that the proposed design incurs the least degradation in output quality as we increase the configurability factor, as compared to other designs