An Empirical Model Based Optimal Architecture for N-Bits M-Points Fast Fourier Transform

Abstract

The use and vast implementation of Discrete Fourier Transform has revolutionized the world and allowed the researchers to think of the modern world from a different perspective. The discovery of Fast Fourier Transform has laid the foundation of an entirely new dimension to the modern world. Keeping in view its utmost importance in the future industry researchers tried to design its hardware architecture as per the requirement of the application. Several architectures have been proposed time to time with new inventions in the previous designs. Some architectures consider clock rate, some take architectural area into consideration, some focuses on parallel execution of the algorithm, so on and so forth. Considering all these inputs to the industry that has been a part to modern world time to time, this research presents an empirical model based upon the optimal architectures for Fast Fourier Transform algorithm for n-bits m-points input. This empirical model is obtained by making several architectures and their respective characteristics are obtained. The data obtained is then passed through a machine learning algorithm known as Regression Algorithm. Linear, quadratic and cubic regression technique is applied to achieve the hierarchy of the designed architectural parameters and this intern will provide us with the empirical models of the architecture. This model will provide us with the specifications of the futuristic architecture that mainly depends upon the one’s requirement i.e. either one considers a single parameter or a tradeoff between different hardware parameters. The parameters that are mainly considered are number of Slice LUT’s, LUT FF Pairs, clock rate, number of processing elements and number of clock cycles required. This proposed methodology can be applied to any hardware architectural designs for analysis and generation of empirical models.