Implementation of Mo soft core in FPGA

Abstract

M0 core developed by ARM is a widely used general purpose processor. M0 core is a RISC based processor utilizing only 12000 logic gates in its small configuration. This makes it very feasible for low powered devices as the power ratings are really low. We can utilize M0 core as a coprocessor providing communication services, crypto graphical services, malware detection services, wireless sensor nodes etc. ARM Cortex M0 core is a propriety processor and has a few limitations of its own. As a propriety core the details of its architectures are not published. Also interfacing of the memory (RAM, ROM) and UART needs to be done to use it for a specific application. In our work we comprehensively study the architecture of M0 core. We thoroughly investigated the Bus (AHB Lite) of M0 core in order to interface it with the RAM and ROM. We were able to successfully interface the Bus with the memories. Four Blocks of 8x2048 Bits RAMs are designed. We also interfaced the Peripheral bus (APB) for UART. Our experiment demonstrated successful transmission of data. For our experiment we used the Xinlinx Spartan 3- E kit to port Cortex M0 processor on FPGA. Xinlinx FPGA XC3S1600E with 33,000 logic gates are enough to port Cortex M0 soft core. In order to visualize results Digital Clock Manager (DCM) is used to scale down 50 MHz clock frequency to 5MHz.