A Model-driven Framework to simplify the generation of UVM-Compliant Testbenches for Early Design Verification Embedded Systems

Abstract

In past era, design and verification complexity of embedded system has been significantly increased. Furthermore, embedded systems have gained enormous attention of industrial experts and researchers due to excessive use in disciplines i.e. IoT, healthcare and automotive systems etc. Embedded system design verification is a difficult task due to its temporal characteristics. Hence, it urges to perform verification in early phases of development to save time and cost. Therefore, complex verification requirements of embedded systems require a simple and reusable solution. Model-Driven Engineering (MDE) provides reusable solutions for simplifying embedded systems design and verification activities. MDE provides capability of modeling design at higher abstraction level. These higher abstraction models are later transformed into low level RTL (Register Transfer Level) code i.e. Verilog, SystemVerilog etc. However, verification of low level RTL code is achieved via simulation. But, testbenches required to perform simulation are written manually at the lower abstraction level, consequently creating a significant gap between design and verification. Therefore, there is a dire need to develop a higher abstraction layer to allow modeling of testbenches at the same level of system design modeling. To bridge the aforementioned verification gap, we have proposed Model-Driven Framework for UVM-compliant Testbenches (MFUT). MFUT enables easy modeling of UVM-compliant testbenches. In the first step, a Unified Modeling Language (UML) Profile (i.e. UML Profile for Testbenches in UVM (UTU)) is developed by extending UML-metamodel to adapt to the concepts of UVM framework. Secondly, a transformation engine, named Model-Driven UVM Transformation Engine (MUTE), is developed using Acceleo. MUTE performs Model-to-Text (M2T) transformation to automatically generate the UVM testbench code i.e. SystemVerilog. Finally, we validated our proposed framework against three extensive case studies i.e. Memory Model, Advance Peripheral Bus and Adder. The experimental results prove that the proposed framework provides an easy and reusable UVM testbench development solution at higher level of abstraction by reducing the complexity and cost of development.