A Framework for Dynamic Partial Reconfiguration of Xilinx 7 Series FPGA-SOC

Abstract

Dynamic Partial reconfiguration is extensively used for applications which requires the adaptive behavior of a system at run time. Almost all SRAM-based field programmable gate arrays (FPGAs) introduced in the last decade, supports partial re-configuration (PR). Resource utilization in the FPGAs can optimized using partial reconfiguration. Most of the resource hungry algorithms comprises of multiple steps which are implemented as separate modules in FPGAs. these modules are usually not used concurrently. Therefor all those modules are never required to be present in the FPGA at the same time. Partial reconfiguration allows to utilize the hardware resource of one module by the other. Partial reconfiguration is ideal for applications which require huge number of computations and can afford a reasonable time to achieve this with a smaller/cheaper FPGA device. These techniques have been studied in detail but their use is yet not very famous in the industry. The goal this research is to design a framework which will allow to take advantage of the hardware architecture and integrate as much logic as possible without using extra hardware resource. A design example of jpeg compression is used to demonstrate the procedure involved in the utilization of technique and to show the advantages that can be achieved with the help of dynamic and partial reconfiguration-based framework. In addition, the effectiveness of the proposed methodology is quantified by comparing the FPGA resource utilization of the original JPEG compression design and that of the partial reconfigurable prototype.