Abstract:
In Electronics World processors are brains and can be implemented as soft core at FPGAs or
ASICs for specific applications.M0 core developed by ARM because of its specifications and
speed is a widely used general purpose processor in industrial and military applications. Mo core
because of its upward compatibility, RISC architecture and utilizing the 12000 logic gates in its
small configuration makes it very feasible to be implemented for various tasks. Because of its low
power rating low its use in low power devices is very much appropriate. . We can utilize M0 core
as a co-processor providing communication services, crypto graphical services, malware detection
services, wireless sensor nodes etc. ARM Cortex M0 core is a propriety processor and has a few
limitations of its own. As a propriety core the details of its architectures are not published. Also
interfacing of the memory (RAM, ROM) and UART needs to be done to use it for a specific
application. In our work we comprehensively study the architecture of M0 core. We thoroughly
investigated the Bus (AHB Lite) of M0 core in order to interface it with the RAM and ROM. We
were able to successfully interface the Bus with the memories. Four Blocks of 8x2048 Bits RAMs
are designed. We also interfaced the Peripheral bus (APB) for UART. UART communication is
implemented. Our experiment demonstrated successful transmission of data. For our experiment
we used the Xilinx Spartan 3-E kit to port Cortex M0 processor on FPGA. Xilinx FPGA
XC3S1600E with 33,000 logic gates are enough to port Cortex M0 soft core. In order to visualize
results Digital Clock Manager (DCM) is used to scale down 50 MHz clock frequency to
5MHz.and practically readable data is comings at HyperTerminal with variable baud rate
according to requirement showing practical implementation of coprocessor communicating
successfully.
