WCDMA BASED RECEIVER DESIGN AND IMPLEMENTATION ON FPGA FOR SOFTWARE DEFINED RADIO

Abstract

Software Defined Radio (SDR) is of big importance when it comes to secure communication in hostile environment. In the signal jamming conditions, the effects on the received signal are undesirable. To counter this problem, the signal to be transmitted is spreaded over the entire bandwidth using chip code. The receiver then uses the same code for despreading. Moreover, to counter the undesirable effects of channel, the training sequence is appended with data before transmission. The receiver uses this training sequence to equalize the effects caused by the channel. In this thesis, two parts of receiver of software defined radio have been implemented. It includes CORDIC and Coarse Frequency Estimation. Implementation has been realized on FPGA because communicational algorithms that provide respective solutions are computationally intensive. Chosen algorithms for implementation are well evolved and robust. Detailed design of each of the implementation has been presented along with description. Two designs are given for coarse frequency estimation algorithm; one of them is optimized for area and other is for performance. Moreover, the CORDIC implementation is optimized for both accuracy and area. Numerous fundamental principles of both signal processing and digital system design have also been mentioned as a part of literature review. Detailed results including percentage error, throughput and resource consumption are provided. In conclusion and future work, the parts of the SDR that can work in cascade with implementation are discussed.