Abstract:
The applications of today’s high tech digital world operate on ultra-fast processing speeds and their
hunger for more resource is increasing. Especially in signal processing and communication systems
precision and accuracy are equally important besides the giga hertz frequencies. Implementing
algorithms by using alternate architectures that require least amount of resources as well as minimum
delays has become a must.
FIR filter being the most widely used filter in digital processing applications is a non-ideal filter
whose high orders need to be used in architecture for accuracy. Multiplication is one of the most
resource consuming and time consuming operation in any computation and is the basic part of FIR
filters.
Digital systems usually involve multiplication of constant coefficients with variable data input.
Distributed arithmetic (DA) architecture exploits this fact and provides a multiplier less multiplication
solution to the most computational complex operation. It has been in use with various modifications
for past couple of decades.
The main idea functional behind the distributed arithmetic (DA) architecture is to dig deep up-to bitlevel and pre-compute the possible answer to the multiplication prior to the arrival of the input bits.
These pre-computed values are saved as ROMs and embedded in hardware. This makes multiplication
operation just a matter of selection of correct answer among available values.
The distributed arithmetic (DA) architecture has been studied for resource utilization by designing
and implementing FIR Filters in Verilog and synthesizing for Viretex5 FPGA. Same idea is also used
in single carrier as well as multi carrier digital communication system to study optimization in
resource utilization. Further improvements have also been proposed. Most research is focused on
efficient use of resources on FPGA through implementation.
7
T
