BYTE SYSTOLIC FULLY PARALLEL AES ARCHITECTURE

Abstract

A novel byte systolic fully parallel architecture is proposed for mapping 128-bit AES encryption algorithm. The plain text of 128-bit block is encrypted using the 128-bit key so number of rounds are 10. All the 10 rounds are implemented in parallel by cascading the stages, so the resulting architecture does not reuse the logic resources instead all the computations are in parallel. The proposed architecture works on in-place indexing; a single byte of plain text is input and after the initial latency of 10x16 cycles a byte of cipher text is output in every clock cycle. The novelty of the proposed architecture is more pronounced around in-place indexing. By employing the inplace indexing byte systolic fully parallel architecture best utilizes the memory and works in a lock step manner. The same data memory of each stage is used for next coming frame thus reducing the hardware resources. The technique intelligently removes all the inter and across round dependences by tracing out a single byte so design works in byte systolic fashion. This scheme speeds up the implementation 10x16 times thus increasing the data rate and throughput. The proposed design for AES encryption offers the data rates of 200Mbs while utilizing 2063 slices and 1.6GHz throughput on Xilinx Virtex V xc5v2x5ot. Comparison results clearly show that proposed architecture offers the best tradeoff between area, data rate and throughput.