MATHEMATICAL MODEL BASED OPTIMIZED CUSTOM NETWORK ON CHIP DESIGN

Abstract

System on chip (SoC) architecture has become more popular as the number of components on a given chip increase. The most important aspect of this architecture is the ability to integrate various heterogeneous components on a single architecture, this requires abstraction and modularity. Another important aspect of this architecture is the methods by which the various components communicate with one another. Network on Chip (NoC) architectures attempt to address these aspects by providing various component level architectures with specific interconnection network topologies and routing techniques. The main aim of the thesis is to design an optimal Network on Chip (NoC) architecture for custom based applications e.g. high data rate communication systems, complex pattern recognition and video processing systems etc. The various aspects of NoC like number of processing elements, their placement, interconnects width, packet size etc are to be optimized. For designing, the architecture of NoC will be mathematically modeled using integer, linear, or non linear programming techniques. While the application, to be mapped on the architecture, will be modeled as a graph partitioning problem. The main aim of modeling the application would be to find the placement of process entities on the NoC architecture for optimal performance. The mathematical model will be solved using any off the shelf programming solver like GUSEK, LINDO/LINGO etc. The results of the solver will be parsed to extract the solution and specifying the design of NoC