Abstract:
To increase the throughput of system is the requirement of many designs. Normally for
FPGA based designs pipelining is used to increase the throughput of the system. Pipelining
increases the throughput of the system by introducing multiple inputs in a pipeline.
Pipeline increases latency for single computation. But the total number of outputs per unit
time increases. Pipelining has advantages for the designs which have only feed forward
circuits. The designs where feedback loops also part of the design, pipelining cannot
perform well. In those scenarios, c‐slow is the better approach. C‐slow increases the
throughput of the system even in the presence of feedback loops. C‐slow increases the
throughput by taking the advantage of parallel computation i.e. multiple threads are
executed in parallel. For this purpose each register in the design is replaced with C number
of registers.
