Abstract:
With the massive growth and developments in digitals systems, there is an increasing need of
digital systems that consume lesser power. Low power applications have many potential target
areas including multimedia applications, DSP applications, embedded controllers etc. Especially,
mobile devices focus on low power consumption for longer battery life and usability. Methods
and techniques have been developed on different levels for reducing power consumption in a
digital circuit. The power consumed by a circuit can be divided into static power consumption
and dynamic power consumption. Static power consumption is due to leakage currents in
transistors and comes under the hardware domain. Whereas dynamic power consumption is due
to switching of clock and other signals in the system and comes under the software/algorithmic
domain. Clock gating is one good technique for reducing dynamic power consumption. In this
technique we disable the clock signal to a circuit or a part of it when its functionality is not
required, thus reducing dynamic power consumption. In this thesis, one such method based on
clock gating is proposed. Traditionally, clock gating is a method applied in ASIC domain.
Application of this technique in FPGA domain is relatively new. In this method we apply clock
gating technique on a digital circuit at FSM level. For achieving better results, we have also
leveraged the architectural benefits of the Virtex-5 FPGA device. So, this method is a
combination of clock gating and a suitable device applied on FPGA based circuits. We tested this
method on two circuits, a simple adder/multiplier circuit and more complex MD5 circuit. We
achieved 5% and 7% reduction in dynamic power consumption respectively
