FLOATING POINT DSP ALGORITHMS IMPLEMENTATION USING DEDICATED MULTIPLIERS ON FPGAS

Abstract

The use of FPGAs for the implementation of DSP algorithms is increasing day by day due to improvement in their size and performance. FPGAs are generally good at fixed point arithmetic but they usually prove inefficient in terms of area and space when used for implementation of floating point algorithms. This is due to the fact that floating point algorithms are complex and it has always been hard to implement these on FPGAs, especially multiplication based algorithms. To cater this problem we have proposed a new technique for implementing floating point multiplier on FPGAs in this thesis. The new design methodology helps us to reduce the area utilization on FPGAs which is a major concern while implementing a floating point algorithm. The key point is to use dedicated multipliers available on FPGAs. These multipliers are fixed point multipliers and we have used them for the simple multiplication of mantissa parts of floating point numbers. So, instead of implementing the whole floating point multiplier on FPGA, the idea is to use the built in fixed point multiplier whenever a multiplication is required. All other issues are handled separately, like sign checking, normalization of floating point numbers, pre and post adjustment of exponents, shifting of mantissas by appropriate number of bits and rounding, flags etc. The multiplier is 32-bit and is in accordance with the IEEE-754 floating point standard. This technique helps in the reduction of area utilization while implementing floating point algorithms on FPGAs. As a proof of this argument we have also implemented a FIR filter using this multiplier and got satisfactory results regarding area utilization. In the end a comparison of my results with others has also been made.