IMPLEMENTATION OF A VLIW ARCHITECTURE IN EXPRESSION ADL

Abstract

Aim of the project is to make a VLIW (very large instruction word) processor in an EXPRESSION ADL. Such processors include one or more functional units, each capable of performing a certain class of functions in parallel. Such processors utilize these multiple functional units simultaneously, to execute programs faster. The first step in a top-down validation methodology is to capture the programmable architectures using a specification language. The language should be powerful enough to specify the wide spectrum of contemporary processor, coprocessor, and memory features. I have designed and implemented the Machine Description of a VLIW processor in EXPRESSION Architecture Description Language. Advances in semiconductor technology permit increasingly complex applications to be realized using programmable systems-on-chips (SOCs). Architecture Description Language (ADL) is a computer language used to describe software and/or system architectures. EXPRESSION supports architectural design space exploration for embedded Systems-on-Chip (SOC) and automatic generation of a retargetable compiler/simulator toolkit. A VLIW implementation has capabilities to those of a superscalar processor issuing and completing more then one operation at a time. For the VLIW implementation, the long instruction word already encodes the concurrent operations. The processor implemented in ADL presents us with the opportunity to improve on the short comings in design. Detailed EXPRESSION language manual is also attached with the Thesis for future references. My design includes both processing and control unit.