SIMULATION AND IMPLEMENTATION OF A ROBUST DIRECT SEQUENCE SPREAD SPECTURM COMMUNICATION SYSTEM

Abstract

Reed Solomon codes form an important class of linear cyclic block codes with numerous applications in communications and data storage. This thesis involves investigation and Hardware Description Language (HDL) implementation of Reed Solomon decoding algorithms and code acquisition for Direct Sequence spread spectrum (DSSS) systems. Conventional decoding algorithms which can correct errors up to half the minimum distance include Berlekamp-Massey (BM) and extended Euclidean (eE) algorithms. These algorithms are compared with respect to their hardware complexity, architecture regularity and decoding delay. A series of algorithmic transformations result in a fully systolic architecture for BM algorithm. This reformulated BM algorithm requires fewer hardware resources and reduced critical path delay when compared with architectures for eE algorithms. A parameterized Verilog code generator for Reed Solomon encoder and Berlekamp Massey architecture has been written in Matlab. Alternate RS decoding procedures based upon polynomial interpolation such as Guruswami-Sudan (GS) algorithm and Berlekamp-Welch (BW) algorithm are implemented using Matlab. GS algorithm is a list decoding algorithm which can provide error correction capabilities beyond half the minimum distance. Second part of the thesis deals with synchronization issues in a DSSS with emphasis on Code acquisition. A baseband DSSS transmitter using a PN spreading sequence equipped with read only memory (ROM) based raised cosine filter is implemented. Correct despreading and decoding of data is possible only if the receiver reference sequence and received sequence are properly synchronized. Receiver coarse synchronization is done by parallel search over the code offset space. Cross correlation of these sequences is performed in the frequency domain by exploiting computational efficiency of the Fast Fourier Transform algorithm.