Abstract:
Complexity reduction in FIR filters implies to design techniques used to optimize
performance of an FIR filter circuit by reducing its structural complexity. These optimizations
improve performance parameters like power consumption, total area occupied by the circuit,
when fabricated on a chip and its processing speed. The process involves reducing the
complexity of the filter design and consequently that of the hardware which makes it up.
Filters fabricated with these techniques show improved performance parameters as compared
to conventionally designed ones.
This thesis covers the design of FIR filters using the Common Sub-Expression
Elimination technique, further enhanced by using Linear Programming to automatically
produce filter coefficients in CSD format, using algorithms which maximize commonality of
sub-expressions in filter coefficients. This maximizes reduction in filter design and fabrication
complexity.
