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Implementation & Evaluation of Sha-3 Candidate Grostl on FPGA Platform using Optimized Architectures for High Throughput and Low Area
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| dc.contributor.author | Adnan, Syed Muhammad | |
| dc.date.accessioned | 2023-12-22T05:26:57Z | |
| dc.date.available | 2023-12-22T05:26:57Z | |
| dc.date.issued | 2012 | |
| dc.identifier.uri | http://10.250.8.41:8080/xmlui/handle/123456789/41326 | |
| dc.description | Supervisor: Dr. Arshad Aziz | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Pakistan Navy Engineering College PNEC, Karachi NUST | en_US |
| dc.title | Implementation & Evaluation of Sha-3 Candidate Grostl on FPGA Platform using Optimized Architectures for High Throughput and Low Area | en_US |
| dc.type | Thesis | en_US |
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MS [198]