The compact implementation of SHA -3 Using FPGA

dc.contributor.author	Arshad, Alia
dc.date.accessioned	2024-01-09T10:57:04Z
dc.date.available	2024-01-09T10:57:04Z
dc.date.issued	2014
dc.identifier.uri	http://10.250.8.41:8080/xmlui/handle/123456789/41514
dc.description	Supervisor: Dr. Arshad Aziz	en_US
dc.language.iso	en	en_US
dc.publisher	Pakistan Navy Engineering College ,Karachi	en_US
dc.title	The compact implementation of SHA -3 Using FPGA	en_US
dc.type	Thesis	en_US