Design of a Fault-Tolerant Multilevel Inverter /

Abstract

The increasing adoption of renewable and clean energy technologies within the electric power grid has spurred a keen interest in reliable and efficient multilevel inverter configurations. Among these, the cascaded H-bridge (CHB) inverter has received attention due to its simplicity and scalability. However, concerns regarding the reliability of semiconductor switches have prompted the exploration of fault-tolerant solutions. This research work introduces a novel fault-tolerant CHB topology, which incorporates a modified H-Bridge (MHB) requiring just two additional switches, a capacitor, and a diode. During a fault event, the MHB produces a five-level output and doubles the voltage, effectively compensating for the missing voltage level in the bypassed faulty H-Bridge. By maintaining consistent output voltage levels, this approach ensures continuous system functionality, even in the presence of switch failures. Consequently, it reduces complexity and costs while enhancing power density. Importantly, the proposed MHB can be seamlessly integrated into any multilevel inverter topology, making it a versatile fault tolerant solution. This work provides a comprehensive description of the operational analysis and functioning of the MHB. Simulation and Hardware-in-the-loop (HIL) verification are conducted, alongside the hardware experimental prototype implementation of the seven-level CHB. The results validate the fault-tolerant operation of the proposed topology during switch faults, thereby demonstrating its effectiveness in enhancing the reliability of multilevel inverter systems.