Customized RISC-V Architecture for DSP Applications

Abstract

Abstract This thesis presents a comprehensive analysis of security considerations within the RISC-V open-source instruction set architecture (ISA), highlighting its unique position due to its transparent development model. We look into the specific security challenges that RISC-V faces, owing to its open-source nature, and the various countermeasures that have been implemented to make RISCV secure. These include hardware security mechanisms such as Physical Memory Protection (PMP) and ISA extensions, as well as cryptographic modification in ISA for RISC-V processors against potential vulnerabilities. The study further examines the rise in custom chip designs utilizing the RISCV ISA, underscoring the security implications that accompany this trend. It is noted that commercial versions of RISC-V often incorporate PMP and hardware security extensions to enhance protection. The thesis evaluates the integration of a cryptographic core within the Picorv32 processor, a design choice that, while increasing security, also results in significant area consumption. An innovative approach, the Custom Co-Processor (CCoP) with a custom interconnect for the Picorv32, is also explored. This method involves ISA extensions to support CCoP operations, effectively reducing the code complexity and significantly boosting performance, especially in tasks such as encryption and decryption by offloading these workloads to the co-processor. The integration of these custom instructions not only enhances core performance but also improves the latency of the design, offering a promising solution to the security and efficiency challenges inherent in RISC-V based systems. This thesis serves as a vital resource for professionals and researchers in the field, providing insights into the security landscape of RISC-V processors. It lays the groundwork for future explorations and developments in securing RISC-V based systems, ensuring their flexibility against evolving threats in the digital age.