Co-Processor Design For Image Enhancement Using FPGA

Abstract

The design and creation of a co-processor for image enhancement is demonstrated in this project. The procedure entails creating algorithms in MATLAB, designing hardware in Verilog, creating software in C, and integrating the system in Vivado. The implementation of the histogram equalization and fixed-point conversion algorithms is part of the MATLAB phase. The development of the BRAM module and histogram computation for the programmable logic (PL) component are the main goals of the hardware design phase. On the other hand, the C programming phase of software design concentrates on fixed point conversion and histogram equalization for the processing system (PS). Vivado is used to integrate the IP cores into the system, allowing for seamless communication between the hardware and software elements