Vector Processing Unit Integrated Risc-V Processor

Abstract

The open-source RISC-V instruction set architecture (ISA) is thoroughly examined in this thesis, emphasizing the ISA’s special position as a result of its transparent development process. We investigate the unique security issues that RISC-V has because it is opensource and the several solutions that have been put in place to keep RISC-V secure. ISA extensions and Physical Memory Protection (PMP) are examples of hardware security measures. Cryptographic modifications are also made to ISA to protect RISC-V processors from potential vulnerabilities. The paper highlights the security risks associated with the growing trend of bespoke chip designs that leverage the RISC-V ISA. It also looks at this trend in more detail. It should be noted that to improve security, commercial versions of RISC-V frequently include PMP and hardware security extensions. The dissertation assesses the incorporation of a cryptographic core into the Picorv32 CPU, a design decision that increases security but consumes a large amount of space. A novel method is also investigated, namely the Custom Co-Processor (CCoP) equipped with a customized interface for the Picorv32. By shifting workloads to the co-processor, this technique uses ISA changes to facilitate CCoP operations, thereby lowering code complexity and improving performance significantly—particularly for activities like encryption and decryption. The incorporation of these customized instructions not only improves the design’s latency but also boosts core performance, providing a potential remedy for the efficiency and security issues that come with RISC-V based systems. This thesis serves as a vital resource for professionals and researchers in the field, providing insights into the security of the RISC-V CPU landscape. It establishes the framework for next research and advancements in protecting RISC-V based systems, guaranteeing their adaptability to changing security risks in the digital era.