MEMORY AWARE DVFS FRAMEWORK FOR SPARC BASED LEON3 PROCESSOR

Abstract

This research has proposed hardware modi cation in softcore LEON3 processor based on SPARC V8 Architecture. LEON3 is an open source softcore processor described in VHDL hardware description language, the softcore nature of LEON3 allows high level of recon guration and customization of hardware design so the major contribution of this dissertation is to modify the hardware design to include support for dynamic voltage frequency scaling and a technique to change the system operating frequency at run time during the execution of standard benchmark applications. In addition, this research has also proposed a technique to acquire performance statistics of the processor such as cache hit/miss ratio and number of cycles consumed by the application which in turn can be exploited to recon gure the operating frequency to improve performance of the system. The proposed techniques have been tested on a Xilinx prototyping board XUPV5 and performance statistics have been validated by comparative analysis with LEON3 simulator TSIM.