Optimization of Critical Path Delays in 16-bit RISC Processor

Abstract

This project is about the design of a Floating-Point Unit (FPU), integrating the FPU into the RISC16 processor, and synthesize the FPU design on the Field Programmable Gate Array (FPGA) SPARTON-6 FPGA family. Hence, this project is required to develop an FPU which can perform the operation on floating point numbers especially and increased precision. The development project will start by studying the basics of multiplication, division, and addition on floating point numbers. This project will use the top-down design methodology: system specification, architecture level, and microarchitecture level development. The microarchitecture level will perform unit partitioning of the system and block partitioning of the units. RTL modelling using Verilog will be performed on each block following the units and eventually the complete system [1]. Verification will be made to determine the functionality correctness of FPU. The project will integrate the FPU into the RISC16 pipeline processor and the verification will be carried out to prove the functionality of FPU. At the end of this project, the FPU will be synthesized on the FPGA sparton6 family. In the end, the basic difference between RISC and CISC is given as,