LOCAL BUS INTERFACE

Abstract

A Local Bus Interface Design The concept of local buses is relatively new to the computer world. It is only in the past 5 or 6 years that the concept of local bus architecture has gained popularity due to the introduction of the processor independent PCI Local Bus standard. The Local bus standard puts the devices that require high bandwidths closer to the CPU and makes the communication between the two easy and at a very high clock frequency as compared to the clock frequency of a traditional expansion bus. Keeping in view the growing trend ofthe local bus architecture we have developed our own local bus standard. Our local bus can run on clock speeds comparable to system clock speeds (System clock divided by 2 or System clock divided by four). This allows for fast data transfers between high bandwidth devices like fast LANs and video display devices and the CPU and memory. We have a very flexible arbitration protocol for our Local Bus. The different bus masters arbitrate for the control of the bus using hog limits and a kind of a token ring. The token normally rotates among the different bus masters in a fixed priority manner in which CPU has the highest priority. Another advantage of the hog limits is that they ensure that the access latency for any bus master should not exceed a certain limit. In other words the user can control the access latency of the different bus masters using their hog limits. Our bus architecture also encourages the concurrency of operations. If a external takes control of the local bus to communicate with another external device then in the mean time CPU can keep on doing some other useful work. All these characteristics make our Local bus very much suitable for use in high performance systems. Its features are such that they can be easily adapted according to the changing needs in the future. We have also mapped it onto an FPGA and it works fine. This makes our local bus very cost effective too.