WHITE BOX VERIFICATION TOOL FOR FPGA MAPPED DESIGN

dc.contributor.author	DR SHOAB A KHAN, MUHAMMAD FAISAL AHMAD IMRAN NAJAM ,OMAR MUKHTAR,
dc.date.accessioned	2025-03-24T07:32:35Z
dc.date.available	2025-03-24T07:32:35Z
dc.date.issued	2001
dc.identifier.other	DE-COMP-19
dc.identifier.uri	http://10.250.8.41:8080/xmlui/handle/123456789/51568
dc.description	DR SHOAB AHMED KHAN	en_US
dc.description.abstract	White Box Verification Methodology is being employed these days along with formal testing techniques. The theme is to probe / monitor internal design during verification process. The tool employed is 0in Checkerware White Box Verification. The idea proposed was that same methodology could be adapted while FPGA based components are being tested. We've just to translate Oin Checkers to synthesizable RTL code. The very document is the report of design of a tool named as Oif WhiteBox Verification for FPGA. This tool helps in the verification of FPGA.	en_US
dc.language.iso	en	en_US
dc.publisher	College of Electrical & Mechanical Engineering (CEME), NUST	en_US
dc.title	WHITE BOX VERIFICATION TOOL FOR FPGA MAPPED DESIGN	en_US
dc.type	Project Report	en_US