MULTI LAYER MULTI PROCESSOR SYSTEM CONTROLLER FOR COMPUTATION-INTENSIVE HIGHLY DENSE APPLICATIONS

Abstract

Complex architectures are required to implement future digital systems. These may include several processors organized around a hierarchical bus structure using a distributed memory structure. Whereas Multi-processor architecture on chip is an emerging issue, several telecom and multi-media applications have generated multiprocessor designs. The present effort is to architect a controller that is capable of handling such a computation-intensive highly dense application.