Abstract:
The purpose of this system was to develop a software programmable
test-pattern generator, receiver, and analyzer capable of meeting the
stringent error-performance requirements of digital transmission facilities.
The system should be capable of monitoring traffic on a network, collect
information such as packets, the number of packets, error packets,
generating and detecting digital patterns for analyzing and trouble-shooting.
The most important features were that it should be able to load a file
from LAN based interface that is PC and transmit it to end user in the form
of E1 stream. Similarly it should be able to sniff data from data stream and
store it. Because of LAN based control, this gives it a very mobile outlook.
The main design is implemented on FPGA with different challenges
like metastability, dual clock synchronization, debugging and testing
hardware. The FPGA is controlled by a microcontroller with the constraint
that Ethernet data rate is considerably faster than serial port interface of
controller. Use of a appropriate data rate converter provides a suitable
solution.
Because of the hardware nature of this project, testing was of
paramount importance. Testing was done in modular manner with unit,
block and integration techniques.
