A FRAMEWORK TO DEVELOP NETWORK ON A CHIP FOR SIGNAL PROCESSING APPLICATIONS

Abstract

In Multi-Processor-System-On-Chip (MpSoC), applications are executed which utilize parallel processing. On-board multiprocessor communication is mostly based on bus masters and bus controllers. This communication approach is a feasible solution for low speed systems. However for applications which require constant transfer of data between processors across the board, it would require either dedicated connections or additional bus-controllers, which consequently increase the complexity of the bus architecture. In a network-on-chip approach, the communication is partitioned into communication layers and provides a structured way of realizing interconnections. Thus the limitations of a bus-based solution are overcome. Our project is design a of a network-on-chip which partitions the communication of a system into layers for maximum reuse and also provides a high level abstraction for the underlying communication framework. The network designed is topology independent and we have also developed a user based tool which helps the user in defining a network of switches of their own choice.