HIGH SPEED CRYPTO ENGINE BYTE SYSTOLIC FPGA IMPLEMENTATION OF AES

Abstract

AES is the first publically accessible and open cipher approved by the National Security Agency. It is based on substitution-permutation network with a fast software and hardware implementation. It’s adopted from the Rijndael algorithm. AES cipher is specified as a number of repetitions of transformation rounds that convert the input plaintext into the final output of cipher text while all AES calculations are carried out in a special finite field. The architecture we have proposed for the implementation of an 8 bit systolic AES architecture for moderate data rate applications thesis which was presented by Dr. Shoaib.A.Khan, Sheikh Muhammad Farhan and Habibullah Jamal. The highlight of the architecture is that it’s a transformation technique for mapping a word bit wide algorithm to byte vector serial architecture. This design offers moderate data rates in the range of 41 Mbps for encryption and 37 Mbps for decryption. If we compare it to other 8-bit designs we see a considerably better performance. The architecture as mentioned above had a limitation. It introduced a delay of 5 cycles after each round of the Rijndael algorithm and this delay has been overcome by the coding techniques. We claim to achieve one of the most high speed encryption/decryption implementations of AES with the help of this architecture.