HARDWARE IMPLEMENTATION OF TIME SYNCHRONIZED l

Abstract

Keeping in mind the requirements of the communication system for the modern world, CPM we have chosen as the modulation scheme, AES for security, BCH for error proofing and FPGA as the hardware platform. This project namely, “Hardware implementation of (time synchronized) incoherent C.P.M. based transceiver providing secure and error prone communication” is a collection of various modules. The developed system is implemented in a way to work for both coherent and non-coherent scenarios. To achieve each mentioned property of the communication system, a different approach/methodology has been implemented. At the transmitter end, for making the conversation/communication secure and error prone an encryption module (AES) has been integrated in the design along with a forward error correction (BCH) module. Next to these, a transmitter module is attached which transmits a waveform of pre-determined length, corresponding to the bit being sent. Synchronization (phase and frequency) has been achieved, at the receiver end, by implementing the phase locked loop. PLL (phase locked loop) makes use of the feed-back phenomena and calculates the degree of error between the original and predicted signal and adjusts the predicted signal to an angle proportional to the degree of error. Its basic task is to predict signal‟s phase and frequency in a non-coherent channel environment i.e. when the carrier is not known. Time synchronization has been achieved by making use of the pilot bits, which provide us with the best sampling instant i.e. the most accurate time to pick up a sample, so that the message received is exactly similar to the one sent. Timing synchronization helps to overcome any timing jitters that might be introduced due natural phenomenon such as refraction, reflection and diffraction. Once the message has been received, it is passed on to the error correction and decryption modules to extract the true message without errors.