Hardware implementaion of OFDM on FPGA for SDR applications

Abstract

The project is to develop a digital communication system that would implement OFDM on FPGA. The system would be able to transmit and receive voice or data between two separate FPGA kits. It handles all the baseband processing of an OFDM system and an RF Front-end could be connected for wireless transmission. The aim of the project is to establish a system that would be able to communicate at higher data rates. The FPGA is specifically being used for its fast, real-time processing capabilities along with the efficient high speed RAM made up of flip-flops and logic gates. A prototype code of the OFDM system has been established using Verilog HDL. The prototype includes various OFDM blocks with specifications of 802.11a standard. It incorporates a 16-point FFT block and a 2/3 convolutional encoder. The FPGA used for implementation is Xilinx Spartan 3E 1600K. The developed prototype has been tested on software by simulating it on the Xilinx ISE suite11.1 and the results were in accordance with the theoretically calculated ones. A bit stream is introduced as an input signal in place of audio data for testing purposes. The developed code was also synthesized using the Xilinx environment to make sure that the required resources do not exceed the available ones. The Code was tested successfully on the hardware after the implementation of the code on FPGA and the data has been transmitted over a wired medium. Voice is fed as an input at the transmitter end and recovered back at the receiver end.