Abstract:
Information security has become a critical concern for Internet users these days. The project ―IP Packet Handling Engine‖ has been designed and implemented to fulfill this dire need by providing a hardware architecture platform for secure IP Communications. The developed handling engine exploits the inherent parallelism feature of FPGAs and implements AES-128 Encryption algorithm in CTR mode to provide a 100% secure hardware solution for IP based communications. The Ethernet Core of FPGAs, along with the encryption codes designed in Verilog (HDL), can be programmed in any FPGA to provide a portable IP Packet Handling Engine. The engine encrypts the outgoing traffic to prevent eavesdroppers from viewing sensitive information. For incoming traffic however, the engine first verifies the source, and then decrypts the packets using the shared secret key. The IP Packet Handling Engine is an easily configurable, cost-effective, and hack immune solution for organizations intending to communicate securely and confidentially over the internet.
