On Fast Implementation of Eta-T Pairing on FPGAs

Abstract

The big challenge in an online transaction is the distribution of secret keys in a secure way as it is the core feature of any security system. With advance- ment in technology and recent security threats there is a need to develop a secure and long term solution for key sharing. Currently, concept of pairing in cryptography is emerging to share the key between the users. Pairing over elliptic curves proves much resilient against most of the attacks. It is efficiently computed in a single round compared to two round Diffie-Hellman key exchange protocol. Eta-T is the most efficient and widely used pair- ing algorithm based on elliptic curves. In this thesis, our work is based on hardware accelerator for Pairing by using FPGAs platform. We align parts of pairing algorithm to be executed in parallel saving number of clock cy- cles. We work on efficient computation of finite field arithmetic operators like multiplication to achieve reduced critical paths. We implement Karatsuba multiplier for multiplying two operands in parallel and then its reduction in the same clock cycle. We implement Adder, Multiplier and Cube over F97 3 . Our implementation calculates Eta-T pairing in just 36.4 μS by consuming 3597 clock cycles which proves to be 25% less in number of clock cycles than contemporary implementations in FPGAs. We provide a fair comparison of our results with state of the art implementations at the end.