Abstract:
Due to technological advancements, tampering has become one of the most addressed issue in industrial world. The objective of tamper evident design is to make a device resistant to all possible tamper events. This report describes possible techniques to make a system tamper evident. It is integrated with firewall implemented on Field Programmable Gate Array chip (FPGA) and deals with the physical tampering of the system. Design scheme consists of modules both external and internal to FPGA. It also describes authorization mechanism for the system. This project meet level 2 and level 3 of Federal Information Processing Standard (FIPS) 140-2 issued by National Institute of Standards and Technology (NIST). In future we will work on level 4 of FIPS 140-2 Standard. It involves fault induction, power analysis and side channel attacks.
