Abstract:
It is an important duty of every IT organization to provide sufficient
security in computer and telecommunication systems thus protecting IP
(intellectual property). Application data is vulnerable during transmission
and storage so solutions for its protection have been developed, however
less consideration has been paid to protect the FPGA configuration data.
This research based project concerns itself mainly with the protection of
the device against all kinds of physical tampering in conformity with the
level 3 of Federal Information Processing Standards (FIPS) 140-2. FIPS
publications are issued by the National Institute of Standards and
Technology (NIST).In order to cover a broad spectrum of possible
applications and environments, this standard proposes four growing
qualitative levels of security. This project implements Level 3 of the FIPS
140-2 standard. It provides certain physical security techniques to avert
any unauthenticated user from accessing the Critical Security Parameters
(CSPs) held within the cryptographic unit. When the detachable covers or
doors of the cryptographic unit are interfered with the intent of an
intrusion, this tamper response technique,zeroize all CSPs. Some of the
implemented techniques use different FPGA features while others are
developed using user logic. The simulations match with the results
observed through ChipScope Pro. All of the modules are implemented on
the Xilinx ML605 Virtex 6 (XC6VLX240T) FPGA kit.
