Abstract:
Biometric authentication is using world widely for different applications in security, attendance metering and for surveillance. Hand vein biometric system is mostly not used widely due to limited resources of machine. In order to overcome resource-constraints. This paper proposes novel method to implement canny edge detection algorithm for extraction vein patterns using CoreGen. The proposed algorithm is implemented on Field programmable Gated Array (FPGA) device. The proposed algorithm improves the False Acceptance Rate (FAR) as compared to existing algorithm while recognition speed is also measured.
This is a novel implementation of a canny edge detector that takes advantage of 4-pixel parallel computation. It is a pipelined architecture that uses on-chip BRAM memories to cache data between the different stages. The exploitation of both hardware parallelism and pipelining creates a very efficient design that has the same memory requirements as a design without parallelism in pixel computation. This results in achieving increased throughputs for high resolution images and a computation time of 3.09ms for a 1.2Mpixel image on a Spartan-6 FPGA. We present synthesis and simulation results for low-end and high-end Xilinx FPGAs and have achieved higher speeds, better throughputs and efficiency than the implementations presented above.
